CJEE

Chinese Journal of Electrical Engineering ›› 2024, Vol. 10 ›› Issue (2): 116-125.doi: 10.23919/CJEE.2024.000061

• Regular Papers • Previous Articles    

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Design and Manufacture of Dual-gate DDSCR with High Failure Current and Holding Voltage*

Xingtao Bao1,2, Yang Wang3, Yujie Liu1,2, Xiangliang Jin1,2,*   

  1. 1. School of Physics and Electronics, Hunan Normal University, Changsha 410081, China;
    2. Key Laboratory of Physics and Devices in the Post-Moore Era, Hunan Normal University, Changsha 410081, China;
    3. School of Integrated Circuits, Peking University, Beijing 100871, China
  • Received:2023-08-22 Revised:2023-10-25 Accepted:2023-12-28 Online:2024-06-25 Published:2024-07-01
  • Contact: * E-mail: 21325718@qq.com
  • About author:Xingtao Bao received the B.E. degree from the School of Computer and Information Science at the Central South Forestry University. He is currently pursuing a graduate degree at the School of Physics and Electronic Science, Hunan Normal University, Changsha, China. His research interests include on-chip electrostatic-discharge protection designs.
    Yang Wang is currently conducting postdoctoral research at the School of Integrated Circuits, Peking University, and his research direction is on-chip ESD protection design.
    Yujie Liu received the B.E. from the School of Information Engineering at Shaoyang University. He is currently pursuing a graduate degree at the School of Physics and Electronic Science, Hunan Normal University, Changsha, China. His research interests include on-chip electrostatic-discharge protection designs.
    Xiangliang Jin (M’12) received the M.S. degree in Microtechnology with an emphasis on electric circuits from Hunan University, Changsha, China, in 2000, and the Ph.D. degree in Microelectronics and Solid-state Circuits with an emphasis on CMOS image sensor design from the Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China, in 2004. After graduation, he established Superpix Micro Technology, Ltd., as a co-founder. From 2010 to 2017, he was a full-time Professor at Xiangtan University. He is currently a Professor at the Hunan Normal University.
  • Supported by:
    *National Natural Science Foundation of China (62174052).

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Abstract: High-voltage controller area network (CAN) buses have a harsh working environment and require a robust electrostatic discharge (ESD) design window. Thus, ordinary silicon-controlled rectifier (SCR) devices do not satisfy these design requirements. To streamline the design and manufacturing of SCRs, this study proposes a novel dual-gate dual-direction SCR (DG-DDSCR) with a high failure current and holding voltage. First, four polysilicon gates, GateA1, GateA2, GateC1, and GateC2, were introduced to the N+ and P+ middle regions of the anode and cathode. When the voltage acts on the anode, the electric field generated by the polysilicon gate strengthens the SCR current path while promoting the release of ESD current in the substrate path. Specifically, the holding voltage of the DG-DDSCR and failure current derived from the test results of a transmission line pulse (TLP) are 29.4 V and 16.7 A, respectively. When the clamping voltage was 40 V, the transient current release of the structure can reach 11.61 A, which met the specifications of the CAN bus ESD window and was suitable for the ESD protection of the target application.

Key words: High failure current, high holding voltage, CMOS technology, dual-direction SCR, gate controlled device